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PowerPC 405GP Embedded Processor Data Sheet
Features
* IBM PowerPC 405 32-bit RISC processor core operating up to 266MHz * PC-133 synchronous DRAM (SDRAM) interface - 32-bit interface for non-ECC applications - 40-bit interface serves 32 bits of data plus 8 check bits for ECC applications * 4KB on-chip memory (OCM) * External peripheral bus - Flash ROM/Boot ROM interface - Direct support for 8-, 16-, or 32-bit SRAM and external peripherals - Up to eight devices - External Mastering supported * DMA support for external peripherals, internal UART and memory - Scatter-gather chaining supported - Four channels * PCI Revision 2.2 compliant interface (32-bit, up to 66MHz) - Synchronous or asynchronous PCI Bus interface - Use internal or external PCI Bus Arbiter * Ethernet 10/100Mbps (full-duplex) support with media independent interface (MII) * Programmable interrupt controller supports seven external and 19 internal edge triggered or level-sensitive interrupts * Programmable timers * Two serial ports (16550 compatible UART) * One IIC interface * General purpose I/O (GPIO) available * Supports JTAG for board level testing * Internal processor local Bus (PLB) runs at SDRAM interface frequency * Supports PowerPC processor boot from PCI memory
Description
Designed specifically to address embedded applications, the PowerPC 405GP (PPC405GP) provides a high-performance, low-power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation requirements. This chip contains a high-performance RISC processor core, SDRAM controller, PCI bus interface, Ethernet interface, control for external ROM and peripherals, DMA with scatter-gather support, serial ports, IIC interface, and general purpose I/O. Technology: IBM CMOS SA-12E, 0.25 m (0.18 m Leff) Package: 456-ball (35mm or 27mm), or 413-ball (25mm) enhanced plastic ball grid array (E-PBGA) Power (typical): 1.5W at 200MHz, 2W at 266MHz
While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
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PowerPC 405GP Embedded Processor Data Sheet
Contents
Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Address Map Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 On-Chip Memory (OCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PLB to PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 10/100 Mbps Ethernet MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Signal List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Tables
System Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Signals Listed by Ball Assignment--413-Ball Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Signals Listed by Ball Assignment--456-Ball Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 I/O Specifications--All speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 I/O Specifications--200MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 I/O Specifications--266MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 PPC405GP Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
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PowerPC 405GP Embedded Processor Data Sheet
Figures
PPC405GP Embedded Controller Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 25mm, 413-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 27mm, 456-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 35mm, 456-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5V-Tolerant Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3
PowerPC 405GP Embedded Processor Data Sheet
Ordering, PVR, and JTAG Information
Processor Frequency 200MHz 200MHz 200MHz 200MHz 200MHz 200MHz 266MHz 266MHz 266MHz 266MHz 266MHz 266MHz Rev Level E E E E E E E E E E E E
Product Name PPC405GP PPC405GP PPC405GP PPC405GP PPC405GP PPC405GP PPC405GP PPC405GP PPC405GP PPC405GP PPC405GP PPC405GP
Order Part Number1 IBM25PPC405GP-3BE200C IBM25PPC405GP3BE200CZ IBM25PPC405GP-3DE200C IBM25PPC405GP-3DE200CZ IBM25PPC405GP-3EE200C IBM25PPC405GP-3EE200CZ IBM25PPC405GP-3BE266C IBM25PPC405GP-3BE266CZ IBM25PPC405GP-3DE266C IBM25PPC405GP-3DE266CZ IBM25PPC405GP-3EE266C IBM25PPC405GP-3EE266CZ
Package 35mm, 456 E-PBGA 35mm, 456 E-PBGA 27mm, 456 E-PBGA 27mm, 456 E-PBGA 25mm, 413 E-PBGA 25mm, 413 E-PBGA 35mm, 456 E-PBGA 35mm, 456 E-PBGA 27mm, 456 E-PBGA 27mm, 456 E-PBGA 25mm, 413 E-PBGA 25mm, 413 E-PBGA
PVR Value 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145 0x40110145
JTAG ID 0x42050049 0x42050049 0x42050049 0x42050049 0x42050049 0x42050049 0x42050049 0x42050049 0x42050049 0x42050049 0x42050049 0x42050049
Note 1: Z at the end of the Order Part Number indicates a tape and reel shipping package. Otherwise, the chips are shipped in a tray.
This section provides the part number nomenclature. For availability, contact your local IBM sales office. The part number contains a part modifier. Included in the modifier is a revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. The PVR (Processor Version Register) is software accessible and contains additional information about the revision level of the part. Refer to the PowerPC 405GP Embedded Processor User's Manual for details on the register content. Order Part Number Key
IBM25PPC405GP-3BE200Cx
Shipping Package Blank = Tray Z = Tape and reel IBM Part Number Operational Case Temperature Range (-40 C to +85 C) Processor Speed 200 MHz 266 MHz Revision Level
Grade 3 Reliability
Package B: 35mm, 456 E-PBGA D: 27mm, 456 E-PBGA E: 25mm, 413 E-PBGA
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PowerPC 405GP Embedded Processor Data Sheet
PPC405GP Embedded Controller Functional Block Diagram
Universal Interrupt Controller Clock Control Reset Timers MMU Power Mgmt DOCM IOCM OCM SRAM DCRs OCM Control GPIO IIC UART UART
PPC405 Processor Core JTAG 8KB D-Cache DCU Trace ICU
DCR Bus
16KB I-Cache
Arb
On-chip Peripheral Bus (OPB)
DMA Controller (4-Channel)
OPB Bridge
MAL
Ethernet
Arb Code Decompression (CodePack)
Processor Local Bus (PLB)
SDRAM Controller
External Bus Controller
External Bus Master Controller
PCI Bridge
13-bit addr 32-bit data
32-bit addr 32-bit data
66 MHz max (async) 33 MHz max (sync)
MII
The PPC405GP is designed using the IBM Microelectronics Blue LogicTM methodology in which major functional blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent way to create complex ASICs using IBM CoreConnectTM Bus Architecture.
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PowerPC 405GP Embedded Processor Data Sheet
Address Map Support
The PPC405GP incorporates two simple and separate address maps. The first address map defines the possible use of address regions that the processor can access. The second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the PPC405GP processor through the use of mtdcr and mfdcr instructions.
System Memory Address Map 4GB System Memory
Function Subfunction SDRAM, External Peripherals, and PCI Memory Note: Any of the address ranges listed at right may be use for any of the above functions.
1
Start Address 0x00000000 0xE8010000 0xEC000000 0xEEE00000 0xEF500000 0xEF900000 0xFFE00000 0xFFFE0000 0xE8000000 0xE8800000 0xEEC00000 0xEED00000 0xEF400000 0xEF600300 0xEF600400 0xEF600500 0xEF600600 0xEF600700 0xEF600800
End Address 0xE7FFFFFF 0xE87FFFFF 0xEEBFFFFF 0xEF3FFFFF 0xEF5FFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xE800FFFF 0xEBFFFFFF 0xEEC00007 0xEED00003 0xEF40003F 0xEF600307 0xEF600407 0xEF60051F 0xEF60063F 0xEF60077F 0xEF6008FF
Size 3712MB 8MB 44MB 6MB 1MB 263MB 2MB 128KB 64KB 56MB 8B 4B 64B 8B 8B 32B 64B 128B 256B
General Use
Boot-up
Peripheral Bus Boot PCI Boot PCI I/O PCI I/O
2
PCI
Configuration Registers Interrupt Acknowledge and Special Cycle Local Configuration Registers UART0 UART1 IIC0 OPB Arbiter GPIO Controller Registers Ethernet Controller Registers
Internal Peripherals
Notes: 1. When peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed above. 2. If PCI boot is selected, a PLB-to-PCI mapping is automatically configured at reset to the address range listed above. 3. After the boot process, software may reassign the boot memory regions for other uses. 4. All address ranges not listed above are reserved.
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PowerPC 405GP Embedded Processor Data Sheet
DCR Address Map 4KB Device Configuration Registers
Function Total DCR Address Space By function: Reserved Memory Controller Registers External Bus Controller Registers Decompression Controller Registers Reserved On-Chip Memory Controller Registers Reserved PLB Registers Reserved OPB Bridge Out Registers Reserved Clock, Control, and Reset Power Management Interrupt Controller Reserved DMA Controller Registers Reserved Ethernet MAL Registers Reserved Notes: 1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register, or 1 kiloword (KW) (which equals 4 KB). 0x000 0x010 0x012 0x014 0x016 0x018 0x020 0x080 0x090 0x0A0 0x0A8 0x0B0 0x0B8 0x0C0 0x0D0 0x100 0x140 0x180 0x200 0x00F 0x011 0x013 0x015 0x017 0x01F 0x07F 0x08F 0x09F 0x0A7 0x0AF 0x0B7 0x0BF 0x0CF 0x0FF 0x13F 0x17F 0x1FF 0x3FF 16W 2W 2W 2W 2W 8W 96W 16W 16W 8W 6W 8W 8W 16W 48W 64W 64W 128W 512W
1
Start Address 0x000
End Address 0x3FF
Size 1KW (4KB)1
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PowerPC 405GP Embedded Processor Data Sheet
On-Chip Memory (OCM)
The OCM feature comprises a memory controller and a one-port 4KB static RAM (SRAM) accessed by the processor core. Features include: * Low-latency access to critical instructions and data * Performance identical to cache hits without misses * Contents change only under program control
PLB to PCI Interface
The PLB to PCI interface core provides a mechanism for connecting PCI devices to the local PowerPC processor and local memory. This interface is compliant with version 2.2 of the PCI Specification. Features include: * Internal PCI bus arbiter for up to six external devices at PCI bus speeds up to 66MHz. Internal arbiter use is optional and can be disabled for systems which employ an external arbiter. * PCI bus frequency up to 66MHz - Synchronous operation at 1/n fractions of PLB speed (n = 1 to 4) to 33MHz maximum - Asynchronous operation from 1/8 PLB frequency to 66MHz maximum * 32-bit PCI address/data bus * Power Management: - PCI Bus Power Management v1.1 compliant * Supports 1:1, 2:1, 3:1, 4:1 clock ratios from PLB to PCI * Buffering between PLB and PCI: - PCI target 64-byte write post buffer - PCI target 96-byte read prefetch buffer - PLB slave 32-byte write post buffer - PLB slave 64-byte read prefetch buffer * Error tracking/status * Supports PCI target side configuration * Supports processor access to all PCI address spaces: - Single-byte PCI I/O reads and writes - PCI memory single-beat and prefetch-burst reads and single-beat writes - Single-byte PCI configuration reads and writes (type 0 and type 1)
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PowerPC 405GP Embedded Processor Data Sheet
- PCI interrupt acknowledge - PCI special cycle * Supports PCI target access to all PLB address spaces * Supports PowerPC processor boot from PCI memory
SDRAM Memory Controller
The PPC405GP Memory Controller core provides a low latency access path to SDRAM memory. A variety of system memory configurations are supported. The memory controller supports up to four physical banks. Up to 256MB per bank are supported, up to a maximum of 1GB. Memory timings, address and bank sizes, and memory addressing modes are programmable. Features include: * 11x8 to 13x11 addressing for SDRAM (2- and 4-bank) * 32-bit memory interface support * Programmable address compare for each bank of memory * Industry standard 168-pin DIMMS are supported (some configurations) * 200 MHz PPC405GP supports up to 100 MHz memory with PC-100 support * 266 MHz PPC405GP supports up to 133 MHz memory with PC-133 support * 4MB to 256MB per bank * Programmable address mapping and timing * Auto refresh * Page mode accesses with up to 4 open pages * Power management (self-refresh) * Error checking and correction (ECC) support - Standard single-error correct, double-error detect coverage - Aligned nibble error detect - Address error logging
External Peripheral Bus Controller (EBC)
* Supports eight banks of ROM, EPROM, SRAM, Flash memory, or slave peripherals * Up to 66MHz operation * Burst and non-burst devices * 8-, 16-, 32-bit byte-addressable data bus width support
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PowerPC 405GP Embedded Processor Data Sheet
* Latch data on Ready, synchronous or asynchronous * Programmable 2K clock time-out counter with disable for Ready * Programmable access timing per device - 0-255 wait states for non-bursting devices - 0-31 burst wait states for first access and up to 7 wait states for subsequent accesses - Programmable CSon, CSoff relative to address - Programmable OEon, WEon, WEoff (0 to 3 clock cycles) relative to CS * Programmable address mapping * Peripheral Device pacing with external "Ready" * External master interface - Write posting from external master - Read prefetching on PLB for external master reads - Bursting capable from external master - Allows external master access to all non-EBC PLB slaves - External master can control EBC slaves for own access and control
DMA Controller
* Supports the following transfers: - Memory-to-memory transfers - Buffered peripheral to memory transfers - Buffered memory to peripheral transfers * Four channels * Scatter/gather capability for programming multiple DMA operations * 8-, 16-, 32-bit peripheral support (OPB and external) * 32-bit addressing * Address increment or decrement * Internal 32-byte data buffering capability * Supports internal and external peripherals * Support for memory mapped peripherals * Support for peripherals running on slower frequency buses
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PowerPC 405GP Embedded Processor Data Sheet
Serial Interface
* One 8-pin UART and one 4-pin UART interface provided * Selectable internal or external serial clock to allow a wide range of baud rates * Register compatibility with NS16550 register set * Complete status reporting capability * Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode * Fully programmable serial-interface characteristics * Supports DMA using internal DMA engine
IIC Bus Interface
* Compliant with Phillips(R) Semiconductors I2C Specification, dated 1995 * Operation at 100kHz or 400kHz * 8-bit data * 10- or 7-bit address * Slave transmitter and receiver * Master transmitter and receiver * Multiple bus masters * Supports fixed VDD IIC interface * Two independent 4 x 1 byte data buffers * Twelve memory-mapped, fully programmable configuration registers * One programmable interrupt request signal * Provides full management of all IIC bus protocol * Programmable error recovery
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PowerPC 405GP Embedded Processor Data Sheet
General Purpose IO (GPIO) Controller
* Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master accesses * 23 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose. The 23 GPIOs are multiplexed with: - 7 of 8 chip selects - All seven external interrupts - All nine instruction trace pins * Each GPIO output is separately programmable to emulate an open-drain driver (i.e., drives to zero, threestated if output bit is 1)
Universal Interrupt Controller (UIC)
The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the various sources of interrupts and the local PowerPC processor. Features include: * Supports seven external and 19 internal interrupts * Edge triggered or level-sensitive * Positive or negative active * Non-critical or critical interrupt to processor core * Programmable critical interrupt priority ordering * Programmable critical interrupt vector for faster vector processing
10/100 Mbps Ethernet MAC
* Capable of handling full/half duplex 100Mbps and 10Mbps operation * Uses the medium independent interface (MII) to the physical layer (PHY not included on chip)
JTAG
* IEEE 1149.1 test access port * IBM RISCWatch debugger support * JTAG Boundary Scan Description Language (BSDL)
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PowerPC 405GP Embedded Processor Data Sheet
25mm, 413-Ball E-PBGA Package
Top View
A1 ball corner
15.7 MAX
C
Note: All dimensions are in mm.
0.20 C 0.25 C
0.20
Bottom View
25.0 22.0
0.35 C
2.223 REF AC AA W U R N L J G E C A 1 3 5 7 9 11 13 15 17 19 21 23 2 4 6 8 10 12 14 16 18 20 22 0.5 0.1 TYP 0.539 REF Thermal balls GLOB TOP 1.00
AB Y V T 25.0 P M K H F D B B
A
0.635 SOLDER BALL x 413 0.30 M C A B 0.10 M C
13
PowerPC 405GP Embedded Processor Data Sheet
27mm, 456-Ball E-PBGA Package
Top View
Ejector Mark 1.80 x 0.10
Small Radius Corner Corresponds to A1 Ball Location Index Mark 1.10 16.00 24.0 REF
00
4.
C
Bottom View
AF AD AB Y V T 27.0 P M K H F D B B
R
0.20
0.
AE AC AA W U R N L J G E C A
10
A
16.00
R 0. 50
C 0.15 C
Note: All dimensions are in mm.
27.0 25.0 0.35 C
1.00
Thermal Balls
1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26
0.45 2.21
0.55 0.15 SOLDERBALL x 456 0.40 s C A s B s 0.20 s C
14
PowerPC 405GP Embedded Processor Data Sheet
35mm, 456-Ball E-PBGA Package
Top View
Reserved Area for Ejector Pin Mark x 4 TYP Corner Shape is Chamferred or Rounded
Gold Gate Release Corresponds to A1 Ball Location
33.5 REF
17.5 TYP
C
Note: All dimensions are in mm.
0.20 35.0 31.75 A
0.20 C 0.25 C 0.35 C
Bottom View
AF AD AB Y V T 35.00.2 P M K H F D B B
AE AC AA W U R N L J G E C A 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 0.65 0.05 SOLDERBALL x 456 0.30 s C A s B s 0.15 s C Thermal Balls
1.27 TYP
Mold Compound
PCB Substrate
0.60.1 2.49 REF 2.65 max
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PowerPC 405GP Embedded Processor Data Sheet
Pin Lists
The PPC405GP embedded controller is available as a 456-ball or a 413-ball E-PBGA package. The 456-ball package is available in two sizes--35 millimeters and 27 millimeters. The 413-ball package size is 25 millimeters. In this section there are three tables that correlate the external signals to the physical package pin (ball) on which they appear. The following table lists all the external signals in alphabetical order and shows the ball number on which the signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate signal in brackets. Multiplexed signals appear alphabetically multiple times in the list--once for each signal name on the ball. The page number listed gives the page in "Signal Functional Description" on page 34 where the signals in the indicated interface group begin.
Signals Listed Alphabetically
Signal Name AVDD BA0 BA1 BankSel0 BankSel1 BankSel2 BankSel3 [BE0]PCIC0 [BE1]PCIC1 [BE2]PCIC2 [BE3]PCIC3 BusReq CAS ClkEn0 ClkEn1 DMAAck0 DMAAck1 DMAAck2 DMAAck3 DMAReq0 DMAReq1 DMAReq2 DMAReq3 DQM0 DQM1 DQM2 DQM3 DQMCB DrvrInh1 DrvrInh2 ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 EMCMDClk EMCMDIO[PHYMDIO] L21 N16 N17 AC19 AB17 AC17 AB14 D16 C22 E23 P23 T1 R15 AB22 Y20 A17 B14 A15 A8 C13 A16 B9 C6 U12 AC5 AC2 AA2 AB13 H17 G17 AA12 AC15 AB12 AC14 AC12 AC10 AC9 AB11 J20 T17
(Part 1 of 10)
Interface Group System SDRAM Page 39 36
413-Ball 456-Ball D25 AB24 AC24 AD17 AF17 AE15 AC14 D19 F24 K24 R26 R3 AB23 AB25 AC25 D16 B15 B14 C12 C16 D14 C11 A7 AC12 AC10 AC6 AA3 AC15 E24 E23 AE14 AF15 AF14 AD13 AF13 AF12 AE13 AD12 H24 AD26
SDRAM
36
PCI External Master Peripheral SDRAM SDRAM
34 38 36 36
External Slave Peripheral
36
External Slave Peripheral
36
SDRAM SDRAM System
36 36 39
SDRAM
36
Ethernet Ethernet
35 35
16
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name EMCTxD0 EMCTxD1 EMCTxD2 EMCTxD3 EMCTxEn EMCTxErr EOT0/TC0 EOT1/TC1 EOT2/TC2 EOT3/TC3 ExtAck ExtReq ExtReset F22 K21 J22 R23 J21 K20 C2 G4 U3 V3 U4 V4 R2
(Part 2 of 10)
Interface Group Ethernet Ethernet Ethernet External Slave Peripheral External Master Peripheral External Master Peripheral External Master Peripheral Page 35 35 35 36 38 38 38
413-Ball 456-Ball J26 L25 L24 P25 K23 K25 F3 G2 V2 Y1 Y3 Y4 T3
GND
A1 A1 A2 A6 A6 A18 A11 A23 A16 C14 D14 A191 F1 A21 F23 A26 J11 B2 J13 B25 K11-K13 B26 L1 C3 L4 C24 L11-L13 D4 M4 D23 M11-M13 E5 M20 E9 N11-N13 E13 N20 E14 N23 E18 Ground P11-P13 E22 Notes: R11 F1 1. Reserved on 27mm package. GND on 35mm package. R13 F26 V1 2. On the 456-ball packages, L11-L16, M11-M16, N11-N16, H11 V23 P11-P16, R11-R16, and T11-T16 are also thermal balls. J5 Y10 3. On the 413-ball package, J11, J13, K11-K13, L11-L13, M11-N13, J22 AA10 N11-N13, P11-P13, R11, and R13 are also thermal balls. L1 AC1 L11-L16 AC6 L26 AC18 M11-M16 AC23 N5 N11-N16 N22 P5 P11-P16 P22 R11-R16 T1 T11-T16 T26 V5 V22 W261 AA1 AA26 AB5
41
17
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name
(Part 3 of 10)
Interface Group Page
413-Ball 456-Ball AB9 AB13 AB14 AB18 AB22 AC4 AC23 AD3 AD24 AE1 AE2 AE25 AF1 AF6 AF81 AF11 AF16 AF21 AF25 AF26 D15 A20 C19 A21 AB18 AC4 AB4 AC3 Y6 T7 H11 G8 D5 C7 D10 B6 C10 U21 Y23 R20 Y22 W21 U20 AA22 AA23 P4 P3 V2 AB3 Y7 U21 Y23 R20 Y22 W21 U20 AA22 C19 D18 C20 A22 AF18 AC9 AE8 AF5 AC7 AB3 C4 C5 A4 B9 B10 A9 B11 V25 V23 W24 W25 Y24 Y25 AA24 AB26 U2 T2 V1 AD6 AE7 V25 V23 W24 W25 Y24 Y25 AA24
Ground Notes: 1. Reserved on 27mm package. GND on 35mm package. 2. On the 456-ball packages, L11-L16, M11-M16, N11-N16, P11-P16, R11-R16, and T11-T16 are also thermal balls. 3. On the 413-ball package, J11, J13, K11-K13, L11-L13, M11-N13, N11-N13, P11-P13, R11, and R13 are also thermal balls. 41
GND
Gnt[PCIReq0] GPIO1[TS1E] GPIO2[TS2E] GPIO3[TS1O] GPIO4[TS2O] GPIO5[TS3] GPIO6[TS4] GPIO7[TS5] GPIO8[TS6] GPIO9[TrcClk] [GPIO10]PerCS1 [GPIO11]PerCS2 [GPIO12]PerCS3 [GPIO13]PerCS4 [GPIO14]PerCS5 [GPIO15]PerCS6 [GPIO16]PerCS7 [GPIO17]IRQ0 [GPIO18]IRQ1 [GPIO19]IRQ2 [GPIO20]IRQ3 [GPIO21]IRQ4 [GPIO22]IRQ5 [GPIO23]IRQ6 Halt HoldAck HoldPri HoldReq IICSCL IICSDA IRQ0[GPIO17] IRQ1[GPIO18] IRQ2[GPIO19] IRQ3[GPIO20] IRQ4[GPIO21] IRQ5[GPIO22] IRQ6[GPIO23]
PCI
34
System
39
System
39
System
39
System External Master Peripheral External Master Peripheral External Master Peripheral Internal Peripheral Internal Peripheral
39 38 38 38 38 38
Interrupts
39
18
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name MemAddr0 MemAddr1 MemAddr2 MemAddr3 MemAddr4 MemAddr5 MemAddr6 MemAddr7 MemAddr8 MemAddr9 MemAddr10 MemAddr11 MemAddr12 MemClkOut0 MemClkOut1 MemData0 MemData1 MemData2 MemData3 MemData4 MemData5 MemData6 MemData7 MemData8 MemData9 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31 AA21 AC22 AA20 AB21 AA19 AB20 AC21 Y16 Y15 AB19 AC20 AA16 AA15 W20 AB23 AC8 AB10 AA11 AC7 AB7 AB9 AB8 AB6 AA9 AA7 Y9 AA6 Y8 AA5 AA4 AB2 Y4 T11 U11 R9 M9 AA3 AB1 Y3 W3 Y2 AA1 T4 R4 W2 Y1 T3
(Part 4 of 10)
Interface Group Page
413-Ball 456-Ball AE22 AC21 AE21 AD21 AF22 AE20 AC19 AE19 AD19 AC18 AF19 AD18 AC17 AC26 AA23 AC13 AE12 AD11 AC11 AF10 AE11 AD10 AF9 AD9 AE9 AD8 AF7 AC8 AD7 AE6 AE5 AE4 AD5 AD4 AC5 AD1 AB2 AA4 AA2 AB1 Y2 W4 W2 W3 V4 W1 V3
SDRAM Note: During a CAS cycle MemAddr0 is the least significant bit (lsb) on this bus.
36
SDRAM
36
SDRAM Note: MemData0 is the most significant bit (msb) on this bus.
36
19
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name A11 D11 G10 G15 H9 H10 H14 H15 J7 J8 J10 J14 J16 J17 K3 K4 K8 K16 L23 N1 P8 P16 P20 P21 R7 R8 R10 R14 R16 R17 T9 T10 T14 T15 U9 U14 Y13 AC13
(Part 5 of 10)
Interface Group Page
413-Ball 456-Ball
OVDD
B171 C131 E6 E7 E8 E19 E20 E21 F5 F22 G5 G22 H5 H22 K21 N241 P31 Output driver voltage U251 Notes: W5 1. Reserved on 27mm package. OVDD on 35mm package. W22 Y5 Y22 AA5 AA22 AB6 AB7 AB8 AB19 AB20 AB21 AD141 AE101
41
20
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PCIAD0 PCIAD1 PCIAD2 PCIAD3 PCIAD4 PCIAD5 PCIAD6 PCIAD7 PCIAD8 PCIAD9 PCIAD10 PCIAD11 PCIAD12 PCIAD13 PCIAD14 PCIAD15 PCIAD16 PCIAD17 PCIAD18 PCIAD19 PCIAD20 PCIAD21 PCIAD22 PCIAD23 PCIAD24 PCIAD25 PCIAD26 PCIAD27 PCIAD28 PCIAD29 PCIAD30 PCIAD31 PCIC0[BE0] PCIC1[BE1] PCIC2[BE2] PCIC3[BE3] PCIClk PCIDevSel PCIFrame PCIGnt0[Req] PCIGnt1 PCIGnt2 PCIGnt3 PCIGnt4 PCIGnt5 PCIIDSel PCIINT[PerWE] PCIIRDY PCIParity PCIPErr PCIReq0[Gnt] PCIReq1 PCIReq2 PCIReq3 PCIReq4 PCIReq5 PCIReset PCISErr B17 B15 B16 B18 A19 C15 C17 C18 C20 D19 A22 B22 D20 H13 M15 D21 G22 H22 G23 L22 M21 J23 M22 K23 N22 M16 T23 P22 N21 U22 R22 V22
(Part 6 of 10)
Interface Group Page
413-Ball 456-Ball A17 B16 C17 A18 D17 C18 B18 A20 B21 A23 D21 B22 B23 C22 C26 F25 K26 L23 M25 M23 N25 M26 N26 P24 R24 R23 P23 R25 T24 U26 T25 V26 D19 F24 K24 R26 B20 H25 J24 U23 T23 F23 H26 N23 M24 P26 C23 J23 E26 G25 C19 C21 B19 A24 G23 J25 B24 G24
PCI Note: PCIAD31 is the most significant bit (msb) on this bus.
34
D16 C22 E23 P23
D17 H20 H21 W23 U23 B23 D23 K22 H23 M23 G13 E22 E21 D22 D15 B21 B20 G16 F20 G21 K14 G20
PCI
34
PCI PCI PCI
34 34 34
PCI
34
PCI PCI PCI PCI PCI
34 34 34 34 34
PCI
34
PCI PCI
34 34
21
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PCIStop PCITRDY PerAddr0 PerAddr1 PerAddr2 PerAddr3 PerAddr4 PerAddr5 PerAddr6 PerAddr7 PerAddr8 PerAddr9 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31 PerBLast PerClk PerCS0 PerCS1[GPIO10] PerCS2[GPIO11] PerCS3[GPIO12] PerCS4[GPIO13] PerCS5[GPIO14] PerCS6[GPIO15] PerCS7[GPIO16] C23 F21 G7 J12 C11 C3 A2 C4 B3 D6 C5 B4 D7 A3 D8 D9 B5 A4 C8 C9 A5 B7 B8 A7 B10 B11 C12 A9 B12 A10 A12 A14 B13 G12 D3 J9 G11 H11 G8 D5 C7 D10 B6 C10
(Part 7 of 10)
Interface Group PCI PCI Page 34 34
413-Ball 456-Ball H23 G26 D5 A3 B4 B5 D6 B6 C6 D7 A5 B7 C7 D8 B8 C8 D9 A8 C9 D10 C10 A10 D11 B12 D13 D12 B13 A12 A13 C14 A14 A15 C15 D15 F2 E4 B3 C4 C5 A4 B9 B10 A9 B11
External Slave Peripheral Note: PerAddr0 is the most significant bit (msb) on this bus.
36
External Slave Peripheral External Master Peripheral
36 38
External Slave Peripheral
36
22
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name PerData0 PerData1 PerData2 PerData3 PerData4 PerData5 PerData6 PerData7 PerData8 PerData9 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerData16 PerData17 PerData18 PerData19 PerData20 PerData21 PerData22 PerData23 PerData24 PerData25 PerData26 PerData27 PerData28 PerData29 PerData30 PerData31 PerErr PerOE PerPar0 PerPar1 PerPar2 PerPar3 PerReady PerR/W PerWBE0 PerWBE1 PerWBE2 PerWBE3 [PerWE]PCIINT PHYCol PHYCrS PHYRxClk [PHYMDIO]EMCMDIO PHYRxD0 PHYRxD1 PHYRxD2 PHYRxD3 PHYRxDV PHYRxErr PHYTxClk R3 W1 U2 T2 U1 P2 N2 M3 R1 M2 P1 M1 K1 J1 L2 M8 H1 K2 L3 G1 G2 J2 H2 F2 E1 J3 G3 D1 J4 F3 D2 H4 H8 K10 L7 F4 E3 C1 L8 H7 D4 B2 B1 E4 G13
(Part 8 of 10)
Interface Group Page
413-Ball 456-Ball U4 U3 U1 T4 R2 P4 R4 P2 R1 P1 N3 N1 M1 N2 M3 M4 N4 M2 L3 L4 K1 L2 K3 J1 K4 J3 J2 J4 H3 G1 H2 H4 B1 C2 D3 G4 G3 E1 E3 C1 D2 E2 F4 D1 C23 AA25 W23 AF20 AD26 AE23 AF23 AC20 AD20 V24 U24 E25
External Slave Peripheral Note: PerData0 is the most significant bit (msb) on this bus.
36
External Master Peripheral External Slave Peripheral External Slave Peripheral External Slave Peripheral External Slave Peripheral External Slave Peripheral External Slave Peripheral Ethernet Ethernet Ethernet Ethernet
38 36 36 36 36 36 36 35 35 35 35
Y21 T20 AA18 T17
AA13 Y19 Y18 Y17 R21 T22 C21
Ethernet Ethernet Ethernet Ethernet
35 35 35 35
23
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name RAS RcvrInh [Req]PCIGnt0 R12 L17 W23 B19 C16 D18 E2 H3 T21 V20 V21 W22 Y51 AA8 AB5
(Part 9 of 10)
Interface Group SDRAM System PCI Page 36 39 34
413-Ball 456-Ball AF24 C25 U23
2
Reserved
A19 B173 C133 D20 H12 Other K23 N243 Notes: 1. Y5 (on the 413-ball package) and AF4 must be tied to OVDD or P33 GND. All other reserved pins should be left unconnected. U253 2. Reserved on 27mm package. GND on 35mm package. W262 3. Reserved on 27mm package. OVDD on 35mm package. Y23 Y26 AF41 AF82 AD143 AE103 A25 AD25 D22 AD22 AE24 AD23 D26 D24 AC22 AB3 AE26 D18 C20 A22 AF18 AC9 AE8 AF5 AC7 AB4 AE18 AE3 AF2 AD15 AD16 AE16 AF3 AC3 AC3 AD2 System System System JTAG JTAG JTAG System System JTAG System JTAG
41
SysClk SysErr SysReset TCK TDI TDO TestEn TmrClk TMS [TrcClk]GPIO9 TRST [TS1E]GPIO1 [TS2E]GPIO2 [TS1O]GPIO3 [TS2O]GPIO4 [TS3]GPIO5 [TS4]GPIO6 [TS5]GPIO7 [TS6]GPIO8 UART0_CTS UART0_DCD UART0_DSR UART0_DTR UART0_RI UART0_RTS UART0_Rx UART0_Tx UART1_CTS/UART1_DSR UART1_DSR/UART1_CTS UART1_DTR/UART1_RTS
H16 P14 J15 U16 U13 T13 E20 L16 U17 T7 T16 A20 C19 A21 AB18 AC4 AB4 AC3 Y6 U7 AA17 P10 T8 AC16 AB15 AA14 U8
39 39 39 39 39 39 39 39 39 39 39
Trace
40
Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral
38 38 38 38 38 38 38 38 38 38 38
N8 N8 N7
24
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed Alphabetically
Signal Name UART1_RTS/UART1_DTR UART1_Rx UART1_Tx UARTSerClk
(Part 10 of 10)
Interface Group Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Page 38 38 38 38
413-Ball 456-Ball
N7
W4 N3 Y14 A13 D12 D13 K9 K15 L9 L10 L14 L15 L20 M10 M14 N4 N9 N10 N14 N15 P9 P15 Y11 Y12 AC11
AD2 AC1 AC2 AE17 E10 E11 E12 E15 E16 E17 K5 K22 L5 L22 M5 M22 R5 R22 T5 T22 U5 U22 AB10 AB11 AB12 AB15 AB16 AB17 AC16
VDD
Logic voltage
41
WE
AB16
SDRAM
36
25
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed by Ball Assignment--413-Ball Package
Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 Signal Name GND PerAddr4 PerAddr11 PerAddr15 PerAddr18 GND PerAddr21 DMAAck3 PerAddr25 PerAddr27 OVDD PerAddr28 VDD PerAddr29 DMAAck2 DMAReq1 DMAAck0 GND PCIAD4 GPIO1[TS1E] GPIO3[TS1O] PCIAD10 GND PerWBE2 PerWBE1 PerAddr6 PerAddr9 PerAddr14 PerCS6[GPIO15] PerAddr19 PerAddr20 DMAReq2 PerAddr22 PerAddr23 PerAddr26 PerAddr30 DMAAck1 PCIAD1 PCIAD2 Ball B17 B18 B19 B20 B21 B22 B23 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 D1 D2 D3 D4 D5 D6 D7 D8 D9 Signal Name PCIAD0 PCIAD3 Reserved PCIReq2 PCIReq1 PCIAD11 PCIGnt2 PerPar3 EOT0/TC0 PerAddr3 PerAddr5 PerAddr8 DMAReq3 PerCS4[GPIO13] PerAddr16 PerAddr17 PerCS7[GPIO16] PerAddr2 PerAddr24 DMAReq0 GND PCIAD5 Reserved PCIAD6 PCIAD7 GPIO2[TS2E] PCIAD8 PHYTxClk PCIC1[BE1] PCIStop PerData27 PerData30 PerBLast PerWBE0 PerCS3[GPIO12] PerAddr7 PerAddr10 PerAddr12 PerAddr13 Ball D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 E1 E2 E3 E4 E20 E21 E22 E23 F1 F2 F3 F4 F20 F21 F22 F23 G1 G2 G3 G4 G7 G8 G10 G11 G12
(Part 1 of 3)
Ball G13 G15 G16 G17 G20 G21 G22 G23 H1 H2 H3 H4 H7 H8 H9 H10 H11 H13 H14 H15 H16 H17 H20 H21 H22 H23 J1 J2 J3 J4 J7 J8 J9 J10 J11 J12 J13 J14 J15 Signal Name PCIINT[PerWE] OVDD PCIReq3 DrvrInh2 PCISErr PCIReq5 PCIAD16 PCIAD18 PerData16 PerData22 Reserved PerData31 PerR/W PerErr OVDD OVDD PerCS1[GPIO10] PCIAD13 OVDD OVDD SysClk DrvrInh1 PCIDevSel PCIFrame PCIAD17 PCIGnt5 PerData13 PerData21 PerData25 PerData28 OVDD OVDD PerClk OVDD GND PerAddr1 GND OVDD SysReset
Signal Name PerCS5[GPIO14] OVDD VDD VDD GND PCIReq0[Gnt] PCIC0[BE0] PCIClk Reserved PCIAD9 PCIAD12 PCIAD15 PCIPErr PCIGnt3 PerData24 Reserved PerPar2 PerWBE3 TestEn PCIParity PCIIRDY PCIC2[BE2] GND PerData23 PerData29 PerPar1 PCIReq4 PCITRDY EMCTxD0 GND PerData19 PerData20 PerData26 EOT1/TC1 PerAddr0 PerCS2[GPIO11] OVDD PerCS0 PerAddr31
26
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed by Ball Assignment--413-Ball Package
Ball J16 J17 J20 J21 J22 J23 K1 K2 K3 K4 K8 K9 K10 K11 K12 K13 K14 K15 K16 K20 K21 K22 K23 L1 L2 L3 L4 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 Signal Name OVDD OVDD EMCMDClk EMCTxEn EMCTxD2 PCIAD21 PerData12 PerData17 OVDD OVDD OVDD VDD PerOE GND GND GND PCIReset VDD OVDD EMCTxErr EMCTxD1 PCIGnt4 PCIAD23 GND PerData14 PerData18 GND PerPar0 PerReady VDD VDD GND GND GND VDD VDD TmrClk RcvrInh Ball L20 L21 L22 L23 M1 M2 M3 M4 M8 M9 M10 M11 M12 M13 M14 M15 M16 M20 M21 M22 M23 N1 N2 N3 N4 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N20 N21 Signal Name VDD AVDD PCIAD19 OVDD PerData11 PerData9 PerData7 GND PerData15 MemData20 VDD GND GND GND VDD PCIAD14 PCIAD25 GND PCIAD20 PCIAD22 PCIIDSel OVDD PerData6 UART1_Tx VDD UART1_RTS/ UART1_DTR UART1_DSR/ UART1_CTS VDD VDD GND GND GND VDD VDD BA0 BA1 GND PCIAD28 Ball N22 N23 P1 P2 P3 P4 P8 P9 P10 P11 P12 P13 P14 P15 P16 P20 P21 P22 P23 R1 R2 R3 R4 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R20 R21 R22 R23
(Part 2 of 3)
Ball T1 T2 T3 T4 T7 T8 T9 T10 T11 T13 T14 T15 T16 T17 T20 T21 T22 T23 U1 U2 U3 U4 U7 U8 U9 U11 U12 U13 U14 U16 U17 U20 U21 U22 U23 V1 V2 V3 Signal Name BusReq PerData3 MemData31 MemData27 GPIO9[TrcClk] UART0_DTR OVDD OVDD MemData17 TDO OVDD OVDD TRST EMCMDIO [PHYMDIO] PHYCrS Reserved PHYRxErr PCIAD26 PerData4 PerData2 EOT2/TC2 ExtAck UART0_CTS UART0_Tx OVDD MemData18 DQM0 TDI OVDD TCK TMS IRQ5[GPIO22] IRQ0[GPIO17] PCIAD29 PCIGnt1 GND HoldReq EOT3/TC3
Signal Name PCIAD24 GND PerData10 PerData5 HoldPri HoldAck OVDD VDD UART0_DSR GND GND GND SysErr VDD OVDD OVDD OVDD PCIAD27 PCIC3[BE3] PerData8 ExtReset PerData0 MemData28 OVDD OVDD MemData19 OVDD GND RAS GND OVDD CAS OVDD OVDD IRQ2[GPIO19] PHYRxDV PCIAD30 EMCTxD3
27
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed by Ball Assignment--413-Ball Package
Ball V4 V20 V21 V22 V23 W1 W2 W3 W4 W20 W21 W22 W23 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Signal Name ExtReq Reserved Reserved PCIAD31 GND PerData1 MemData29 MemData24 UART1_Rx MemClkOut0 IRQ4[GPIO21] Reserved PCIGnt0[Req] MemData30 MemData25 MemData23 MemData16 Reserved GPIO8[TS6] IICSDA MemData12 MemData10 GND VDD VDD OVDD UARTSerClk Ball Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 Signal Name MemAddr8 MemAddr7 PHYRxD3 PHYRxD2 PHYRxD1 ClkEn1 PHYCol IRQ3[GPIO20] IRQ1[GPIO18] MemData26 DQM3 MemData21 MemData14 MemData13 MemData11 MemData9 Reserved MemData8 GND MemData2 ECC0 PHYRxD0 UART0_Rx MemAddr12 MemAddr11 UART0_DCD PHYRxClk Ball AA19 AA20 AA21 AA22 AA23 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22
(Part 3 of 3)
Ball AB23 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 Signal Name MemClkOut1 GND DQM2 GPIO7[TS5] GPIO5[TS3] DQM1 GND MemData3 MemData0 ECC6 ECC5 VDD ECC4 OVDD ECC3 ECC1 UART0_RI BankSel2 GND BankSel0 MemAddr10 MemAddr6 MemAddr1 GND
Signal Name MemAddr4 MemAddr2 MemAddr0 IRQ6[GPIO23] Halt MemData22 MemData15 IICSCL GPIO6[TS4] Reserved MemData7 MemData4 MemData6 MemData5 MemData1 ECC7 ECC2 DQMCB BankSel3 UART0_RTS WE BankSel1 GPIO4[TS2O] MemAddr9 MemAddr5 MemAddr3 ClkEn0
28
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed by Ball Assignment--456-Ball Package
Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 Signal Name GND GND PerAddr1 PerCS3[GPIO12] PerAddr8 GND DMAReq3 PerAddr15 PerCS6[GPIO15] PerAddr19 GND PerAddr25 PerAddr26 PerAddr28 PerAddr29 GND PCIAD0 PCIAD3 Res - 27/GND - 35 PCIAD7 GND GPIO3[TS1O] PCIAD9 PCIReq3 SysClk GND PerErr GND PerCS0 PerAddr2 PerAddr3 PerAddr5 PerAddr9 PerAddr12 PerCS4[GPIO13] PerCS5[GPIO14] PerCS7[GPIO16] PerAddr21 PerAddr24 Ball B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 Signal Name DMAAck2 DMAAck1 PCIAD1 Res - 27/OVDD - 35 PCIAD6 PCIReq2 PCIClk PCIAD8 PCIAD11 PCIAD12 PCIReset GND GND PerR/W PerOE GND PerCS1[GPIO10] PerCS2[GPIO11] PerAddr6 PerAddr10 PerAddr13 PerAddr16 PerAddr18 DMAReq2 DMAAck3 Res - 27/OVDD - 35 PerAddr27 PerAddr30 DMAReq0 PCIAD2 PCIAD5 PCIReq0[Gnt] GPIO2[TS2E] PCIReq1 PCIAD13 PCIINT[PerWE] GND RcvrInh PCIAD14 Ball D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13
(Part 1 of 3)
Ball E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H22 Signal Name GND VDD VDD VDD GND OVDD OVDD OVDD GND DrvrInh2 DrvrInh1 PHYTxClk PCIParity GND PerBLast EOT0/TC0 PerWBE2 OVDD OVDD PCIGnt2 PCIC1[BE1] PCIAD15 GND PerData29 EOT1/TC1 PerPar2 PerPar1 OVDD OVDD PCIReq4 PCISErr PCIPErr PCITRDY Res - 27/GND - 35 PerData30 PerData28 PerData31 OVDD OVDD
Signal Name PerWBE3 PerWBE0 PerPar0 GND PerAddr0 PerAddr4 PerAddr7 PerAddr11 PerAddr14 PerAddr17 PerAddr20 PerAddr23 PerAddr22 DMAReq1 PerAddr31 DMAAck0 PCIAD4 GPIO1[TS1E] PCIC0[BE0] Reserved PCIAD10 SysReset GND TmrClk AVDD TestEn PerPar3 PerWBE1 PerReady PerClk GND OVDD OVDD OVDD GND VDD VDD VDD GND
29
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed by Ball Assignment--456-Ball Package
Ball H23 H24 H25 H26 J1 J2 J3 J4 J5 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L11 L12 L13 L14 L15 L16 L22 L23 L24 L25 L26 Signal Name PCIStop EMCMDClk PCIDevSel PCIGnt3 PerData23 PerData26 PerData25 PerData27 GND GND PCIIRDY PCIFrame PCIReq5 EMCTxD0 PerData20 Res - 27/OVDD - 35 PerData22 PerData24 VDD VDD EMCTxEn PCIC2[BE2] EMCTxErr PCIAD16 GND PerData21 PerData18 PerData19 VDD GND GND GND GND GND GND VDD PCIAD17 EMCTxD2 EMCTxD1 GND Ball M1 M2 M3 M4 M5 M11 M12 M13 M14 M15 M16 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N11 N12 N13 N14 N15 N16 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P11 P12 P13 Signal Name PerData12 PerData17 PerData14 PerData15 VDD GND GND GND GND GND GND VDD PCIAD19 PCIGnt5 PCIAD18 PCIAD21 PerData11 PerData13 PerData10 PerData16 GND GND GND GND GND GND GND GND PCIGnt4 Res - 27/OVDD - 35 PCIAD20 PCIAD22 PerData9 PerData7 Res - 27/OVDD - 35 PerData5 GND GND GND GND Ball P14 P15 P16 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R11 R12 R13 R14 R15 R16 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T11 T12 T13 T14 T15 T16 T22 T23 T24 T25 T26
(Part 2 of 3)
Ball U1 U2 U3 U4 U5 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y22 Y23 Y24 Y25 Y26 Signal Name PerData2 HoldAck PerData1 PerData0 VDD VDD PCIGnt0[Req] PHYRxErr Res - 27/OVDD - 35 PCIAD29 HoldReq EOT2/TC2 MemData31 MemData29 GND GND IRQ1[GPIO18] PHYRxDV IRQ0[GPIO17] PCIAD31 MemData30 MemData27 MemData28 MemData26 OVDD OVDD PHYCrS IRQ2[GPIO19] IRQ3[GPIO20] Res - 27/GND - 35 EOT3/TC3 MemData25 ExtAck ExtReq OVDD OVDD Reserved IRQ4[GPIO21] IRQ5[GPIO22] Reserved
Signal Name GND GND GND GND PCIAD26 PCIAD23 EMCTxD3 PCIIDSel PerData8 PerData4 BusReq PerData6 VDD GND GND GND GND GND GND VDD PCIAD25 PCIAD24 PCIAD27 PCIC3[BE3] GND HoldPri ExtReset PerData3 VDD GND GND GND GND GND GND VDD PCIGnt1 PCIAD28 PCIAD30 GND
30
PowerPC 405GP Embedded Processor Data Sheet
Signals Listed by Ball Assignment--456-Ball Package
Ball AA1 AA2 AA3 AA4 AA5 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 Signal Name GND MemData23 DQM3 MemData22 OVDD OVDD MemClkOut1 IRQ6[GPIO23] PHYCol GND MemData24 MemData21 GPIO9[TrcClk] UART0_CTS GND OVDD OVDD OVDD GND VDD VDD VDD GND GND VDD VDD VDD GND OVDD OVDD OVDD GND CAS BA0 ClkEn0 Ball AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 Signal Name Halt UART1_Rx UART1_Tx UART1_DSR/ UART1_CTS GND MemData19 DQM2 GPIO8[TS6] MemData12 GPIO5[TS3] DQM1 MemData3 DQM0 MemData0 BankSel3 DQMCB WE MemAddr12 MemAddr9 MemAddr6 PHYRxD2 MemAddr1 TMS GND BA1 ClkEn1 MemClkOut0 MemData20 UART1_RTS/ UART1_DTR GND MemData18 MemData17 IICSCL MemData13 MemData10 Ball AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17
(Part 3 of 3)
Ball AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Signal Name UART0_DCD MemAddr7 MemAddr5 MemAddr2 MemAddr0 PHYRxD0 TDI GND TRST GND UART0_DTR UART0_Tx Reserved GPIO7[TS5] GND MemData11 Res - 27/GND - 35 MemData7 MemData4 GND ECC5 ECC4 ECC2 ECC1 GND BankSel1 GPIO4[TS2O] MemAddr10 PHYRxClk GND MemAddr4 PHYRxD1 RAS GND GND
Signal Name MemData8 MemData6 MemData2 ECC7 ECC3 Res - 27/OVDD - 35 UART0_RI UART0_RTS BankSel0 MemAddr11 MemAddr8 PHYRxD3 MemAddr3 TCK TDO GND SysErr EMCMDIO [PHYMDIO] GND GND UART0_DSR MemData16 MemData15 MemData14 IICSDA GPIO6[TS4] MemData9 Res - 27/OVDD - 35 MemData5 MemData1 ECC6 ECC0 BankSel2 UART0_Rx UARTSerClk
31
PowerPC 405GP Embedded Processor Data Sheet
Signal List
The table following table provides a summary of the number of package pins associated with each functional interface group.
Pin Summary
No. of Pins Group
PCI Ethernet SDRAM External peripheral External master Internal peripheral Interrupts JTAG System Total Signal Pins OVDD VDD Gnd Thermal (and Gnd) Reserved Total Pins
413-Ball package 25 mm
60 18 71 96 9 15 7 5 19 300 38 22 26 15 12 413 60 18 71 96 9 15 7 5 19 300 32 24 60 36 4 456
456-Ball Package 35 mm 27mm
60 18 71 96 9 15 7 5 19 300 24 24 56 36 16 456
Multiplexed Pins In the table "Signal Functional Description" on page 34, each external signal is listed along with a short description of the signal function. Some signals are multiplexed on the same package pin (ball) so that the pin can be used for different functions. Multiplexed signals are shown as a default signal with a secondary signal in square brackets (for example, GPIO1[TS1E]). Active-low signals (for example, RAS) are marked with an overline. It is expected that in any single application a particular pin will always be programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. In addition to multiplexing, many pins are also multi-purpose. For example, the EBC peripheral controller address pins are used as outputs by the PPC405GP to broadcast an address to external slave devices when the PPC405GP has control of the external bus. When, during the course of normal chip operation, an external master gains ownership of the external bus, these same pins are used as inputs which are driven by the external master and received by the EBC in the PPC405GP. In this example, the pins are also bidirectional, serving as both inputs and outputs. Intialization Strapping One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only during reset and are used for other functions during normal operation (see "Strapping" on page 55). Note
32
PowerPC 405GP Embedded Processor Data Sheet
that the use of these pins for strapping is not considered multiplexing since the strapping function is not programmable. Pull-Up and Pull-Down Resistors Pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in an appropriate state. The recommended pull-up value of 3k to +3.3V (10k to +5V can be used on 5V tolerant I/Os) and pull-down value of 1k to GND, applies only to individually terminated signals. To prevent possible damage to the device, I/Os capable of becoming outputs must never be tied together and terminated through a common resistor. If your system-level test methodology permits, input-only signals can be connected together and terminated through either a common resistor or directly to +3.3V or GND. When a resistor is used, its value must ensure that the grouped I/Os reach a valid logic zero or logic one state when accounting for the total input current into the PPC405GP. Unused I/Os Strapping of some pins may be necessary when they are unused. Although the PPC405GP requires only the pull-up and pull-down terminations as specified in the "Signal Functional Description" on page 34, good design practice is to terminate all unused inputs or to configure I/Os such that they always drive. If unused, the peripheral, SDRAM, and PCI buses should be configured and terminated as follows: * Peripheral interface--PerAddr0:31, PerData0:31, and all of the control signals are driven by default. Terminate PerReady high and PerError low. * SDRAM--Program SDRAM0_CFG[EMDULR]=1 and SDRAM0_CFG[DCE]=1. This causes the PPC405GP to actively drive all of the SDRAM address, data, and control signals. * PCI--The PCI pull-up requirements given in the Signal Functional Description apply only when the PCI interface is being used. When the PCI bridge is unused, configure the PCI controller to park on the bus and actively drive PCIAD31:0, PCIC3:0[BE3:0], and the remaining PCI control signals by doing the following: - Strap the PPC405GP to disable the internal PCI arbiter and to operate the PCI interface in synchronous mode. - Individually connect PCISErr, PCIPErr, PCITRDY, and PCIStop through 3.3k resistors to +3.3V. - Terminate PCIReq1:5 to +3.3V. - Terminate PCIReq0[Gnt] to GND. External Bus Control Signals All peripheral bus control signals (PerCS0:7, PerR/W, PerWBE0:3, PerOE, PerWE, PerBLast, HoldAck, ExtAck) are set to the high-impedance state when ExtReset=0. In addition, as detailed in the PowerPC 405GP Embedded Processor User's Manual, the peripheral bus controller can be programmed via EBC0_CFG to float some of these control signals between transactions and/or when an external master owns the peripheral bus. As a result, a pull-up resistor should be added to those control signals where an undriven state may affect any devices receiving that particular signal. The following table lists all of the I/O signals provided by the PPC405GP. Please refer to "Signals Listed Alphabetically" on page 16 for the pin number to which each signal is assigned.
33
PowerPC 405GP Embedded Processor Data Sheet
Signal Functional Description
(Part 1 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 33 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 33 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 33.
Signal Name Description I/O Type
Notes
PCI Interface
PCIAD31:0 PCIC3:0[BE3:0] PCI Address/Data Bus. Multiplexed address and data bus. PCI bus command and byte enables. PCI parity. Parity is even across PCIAD0:31 and PCIC0:3[BE0:3]. PCIParity is valid one cycle after either an address or data phase. The PCI device that drove PCIAD0:31 is responsible for driving PCIParity on the next PCI bus clock. PCIFrame is driven by the current PCI bus master to indicate the beginning and duration of a PCI access. PCIIRDY is driven by the current PCI bus master. Assertion of PCIIRDY indicates that the PCI initiator is ready to transfer data. The target of the current PCI transaction drives PCITRDY. Assertion of PCITRDY indicates that the PCI target is ready to transfer data. The target of the current PCI transaction can assert PCIStop to indicate to the requesting PCI master that it wants to end the current transaction. PCIDevSel is driven by the target of the current PCI transaction. A PCI target asserts PCIDevSel when it has decoded an address and command encoding and claims the transaction. PCIIDSel is used during configuration cycles to select the PCI slave interface for configuration. PCISErr is used for reporting address parity errors or catastrophic failures detected by a PCI target. PCIPErr is used for reporting data parity errors on PCI transactions. PCIPErr is driven active by the device receiving PCIAD0:31, PCIC0:3[BE0:3], and PCIParity, two PCI clocks following the data in which bad parity is detected. PCIClk is used as the asynchronous PCI clock when in asynch mode. It is unused when the PCI interface is operated synchronously with the PLB bus. PCI specific reset. PCI interrupt. Open-drain output (two states; 0 or open circuit) or Peripheral write enable. Low when any of the four PerWBE0:3 write byte enables are low. Multipurpose signal, used as PCIReq0 when internal arbiter is used, and as Gnt when external arbiter is used. I/O I/O 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 2
PCIParity
I/O
PCIFrame PCIIRDY
I/O I/O
2 2
PCITRDY
I/O
2
PCIStop
I/O
2
PCIDevSel
I/O
2
PCIIDSel PCISErr
I I/O
PCIPErr
I/O
2
PCIClk
I
5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI
PCIReset
O
PCIINT[PerWE]
O
PCIReq0[Gnt]
I
34
PowerPC 405GP Embedded Processor Data Sheet
Signal Functional Description
(Part 2 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 33 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 33 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 33.
Signal Name PCIReq1:5 Description Used as PCIReq1:5 input when internal arbiter is used. Gnt0 when internal arbiter is used or Req when external arbiter is used. Used as PCIGnt1:5 output when internal arbiter is used. I/O I Type 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI
Notes
PCIGnt0[Req]
O
PCIGnt1:5
O
Ethernet Interface
PHYRxD3:0 EMCTxD3:0 PHYRxErr PHYRxClk Received data. This is a nibble wide bus from the PHY. The data is synchronous with the PHYRxClk. Transmit data. A nibble wide data bus towards the net. The data is synchronous to the PHYTxClk. Receive Error. This signal comes from the PHY and is synchronous to the PHYRxClk. Receiver Medium clock. This signal is generated by the PHY. Receive Data Valid. Data on the Data Bus is valid when this signal is activated. Deassertion of this signal indicates end of the frame reception. Carrier Sense signal from the PHY. This is an asynchronous signal. Transmit Error. This signal is generated by the Ethernet controller, is connected to the PHY and is synchronous with the PHYTxClk. It informs the PHY that an error was detected. Transmit Enable. This signal is driven by the EMAC to the PHY. Data is valid during the active state of this signal. Deassertion of this signal indicates end of frame transmission. This signal is synchronous to the PHYTxClk. This clock comes from the PHY and is the Medium Transmit clock. Collision signal from the PHY. This is an asynchronous signal. Management Data Clock. The MDClk is sourced to the PHY. This clock has a period of 400ns, adjustable via EMAC0_STACR[OPBC]. Management information is transferred synchronously with respect to this clock. Management Data Input/Output is a bidirectional signal between the Ethernet controller and the PHY. It is used to transfer control and status information. I O I I 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1 6 1 1
PHYRxDV
I
1
PHYCrS
I
1
EMCTxErr
O
6
EMCTxEn
O
5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
6
PHYTxClk PHYCol
I I
1 1
EMCMDClk
O
EMCMDIO[PHYMDIO]
I/O
5V tolerant 3.3V LVTTL
1
35
PowerPC 405GP Embedded Processor Data Sheet
Signal Functional Description
(Part 3 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 33 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 33 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 33.
Signal Name Description I/O Type
Notes
SDRAM Interface
Memory data bus. Notes: 1. MemData0 is the most significant bit (msb). 2. MemData31 is the least significant bit (lsb). Memory address bus. Notes: 1. MemAddr12 is the most significant bit (msb). 2. MemAddr0 is the least significant bit (lsb). Bank Address supporting up to 4 internal banks. Row Address Strobe. Column Address Strobe. DQM for byte lane: 0 (MemData0:7), 1 (MemData8:15), 2 (MemData16:23), and 3 (MemData24:31) DQM for ECC check bits. ECC check bits 0:7. Select up to four external SDRAM banks. Write Enable. SDRAM Clock Enable. Two copies of an SDRAM clock allows, in some cases, glueless SDRAM attach without requiring this signal to be repowered by a PLL or zero-delay buffer.
MemData0:31
I/O
3.3V LVTTL
MemAddr12:0
O
3.3V LVTTL
BA1:0 RAS CAS
O O O
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
DQM0:3
O
3.3V LVTTL
DQMCB ECC0:7 BankSel0:3 WE ClkEn0:1 MemClkOut0:1
O I/O O O O O
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
External Slave Peripheral Interface
PerData0:31 Peripheral data bus used by PPC405GP when not in external master mode, otherwise used by external master. Note: PerData0 is the most significant bit (msb) on this bus. Peripheral address bus used by PPC405GP when not in external master mode, otherwise used by external master. Note: PerAddr0 is the most significant bit (msb) on this bus. Peripheral byte parity signals. As outputs, these pins can act as byte-enables which are valid for an entire cycle or as write-byte-enables which are valid for each byte on each data transfer, allowing partial word transactions. As outputs, pins are used by either the pripheral controller or the DMA controller depending upon the type of transfer involved. Used as inputs when an external bus master owns the external interface. I/O 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1
PerAddr0:31
I/O
1
PerPar0:3
I/O
1
PerWBE0:3
I/O
5V tolerant 3.3V LVTTL
1, 7
36
PowerPC 405GP Embedded Processor Data Sheet
Signal Functional Description
(Part 4 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 33 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 33 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 33.
Signal Name Description Peripheral write enable. Low when any of the four PerWBE0:3 write byte enables are low. or PCI interrupt. Open-drain output (two states; 0 or open circuit) Peripheral chip select bank 0. Seven additional peripheral chip selects or General Purpose I/O - To access this function, software must toggle a DCR bit. Used by either peripheral controller or DMA controller depending upon the type of transfer involved. When the PPC405GP is the bus master, it enables the selected device to drive the bus. Used by the PPC405GP when not in external master mode, as output by either the peripheral controller or DMA controller depending upon the type of transfer involved. High indicates a read from memory, low indicates a write to memory. Otherwise it used by the external master as an input to indicate the direction of transfer. Used by a peripheral slave to indicate it is ready to transfer data. Used by the PPC405GP when not in external master mode, otherwise used by external master. Indicates the last transfer of a memory access. DMAReq0:3 are used by slave peripherals to indicate they are prepared to transfer data. DMAAck0:3 are used by the PPC405GP to cause the DMA peripheral to transfer data. End Of Transfer/Terminal Count. I/O Type 5V tolerant 3.3V PCI 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
Notes
[PerWE]PCIINT
O
PerCS0
O
7
PerCS1:7[GPIO10:16]
O[I/O]
1, 7
PerOE
O
5V tolerant 3.3V LVTTL
7
PerR/W
I/O
5V tolerant 3.3V LVTTL
1
PerReady
I
5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
1
PerBLast
I/O
1, 7
DMAReq0:3 DMAAck0:3 EOT0:3/TC0:3
I O I/O
1 6 1
37
PowerPC 405GP Embedded Processor Data Sheet
Signal Functional Description
(Part 5 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 33 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 33 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 33.
Signal Name Description I/O Type
Notes
External Master Peripheral Interface
PerClk ExtReset HoldReq HoldAck ExtReq ExtAck HoldPri BusReq PerErr Peripheral clock to be used by an external master and by synchronous peripheral slaves. Peripheral reset to be used by an external master and by synchronous peripheral slaves. Hold Request, used by an external master to request ownership of the peripheral bus. Hold Acknowledge, used by the PPC405GP to transfer ownership of peripheral bus to an external master. ExtReq is used by an external master to indicate it is prepared to transfer data. ExtAck is used by the PPC405GP to indicate a data transfer cycle. Used by an external master to indicate the priority of a given external master tenure. Used when the PPC405GP needs to regain control of peripheral interface from an external Master. An input used to indicate to the PPC405GP that an external slave peripheral error occurred. O O I O I O I O I 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1, 5 1, 5 6 1 6 1
Internal Peripheral Interface
UARTSerClk Serial Clock used to provide an alternate clock to the internally generated serial clock. Used in cases where the allowable internally generated baud rates are not satisfactory. This input can be individually connected to either UART. UART0 Serial Data In. UART0 Serial Data Out. UART0 Data Carrier Detect. UART0 Data Set Ready. UART0 Clear To Send. UART0 Data Terminal Ready. UART0 Request To Send. UART0 Ring Indicator. I 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1
UART0_Rx UART0_Tx UART0_DCD UART0_DSR UART0_CTS UART0_DTR UART0_RTS UART0_RI
I O I I I O O I
1 6 1 1 1 6 6 1
38
PowerPC 405GP Embedded Processor Data Sheet
Signal Functional Description
(Part 6 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 33 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 33 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 33.
Signal Name UART1_Rx UART1_Tx UART1 Serial Data In. UART1 Serial Data Out. UART1 Data Set Ready or UART1 Clear To Send. To access this function, software must toggle a DCR bit. UART1 Request To Send or UART1 Data Terminal Ready. To access this function, software must toggle a DCR bit. IIC Serial Clock. IIC Serial Data. Description I/O I O Type 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
Notes
1 6
UART1_DSR/ UART1_CTS
I
1
UART1_RTS/ UART1_DTR
O
5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
6
IICSCL IICSDA
I/O I/O
1, 2 1, 2
Interrupts Interface
Interrupt requests or General Purpose I/O. To access this function, software must toggle a DCR bit. 5V tolerant 3.3V LVTTL
IRQ0:6[GPIO17:23]
I[I/O]
1
JTAG Interface
TDI TMS TDO TCK TRST Test data in. JTAG test mode select. Test data out. JTAG test clock. The frequency of this input can range from DC to 25MHz. JTAG reset. TRST must be low at power-on to initialize the JTAG controller and for normal operation of the PPC405GP. I I O I I 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1, 4 5 1, 4 1, 4
System Interface
SysClk Main system clock input. Main system reset. External logic can drive this bidirectional pin low (minimum of 16 cycles) to initiate a system reset. A system reset can also be initiated by software. Implemented as an opendrain output (two states; 0 or open circuit). Clean voltage input for the PLL. I 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
SysReset
I/O
1, 2
AVDD
I
39
PowerPC 405GP Embedded Processor Data Sheet
Signal Functional Description
(Part 7 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 33 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 33 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 33.
Signal Name SysErr Halt Description Set to 1 when a Machine Check is generated. Halt from external debugger. General Purpose I/O or Even Trace execution status. To access this function, software must toggle a DCR bit. General Purpose I/O or Odd Trace execution status. To access this function, software must toggle a DCR bit. General Purpose I/O or Odd Trace execution status. To access this function, software must toggle a DCR bit. General Purpose I/O or Trace status. To access this function, software must toggle a DCR bit. General Purpose I/O or Trace interface clock. A toggling signal that is always half of the CPU core frequency. To access this function, software must toggle a DCR bit. Test Enable. Used only for manufacturing tests. Pull down for normal operation. Receiver Inhibit. Used only for manufacturing tests. Pull up for normal operation. Driver Inhibit 1 and 2. Used only for manufacturing tests. Pull up for normal operation. An external clock input that can be used to clock the timers in the CPU core. I/O O I Type 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1, 2
Notes
GPIO1[TS1E] GPIO2[TS2E]
I/O[O]
1, 6
GPIO3[TS1O]
I/O[O]
5V tolerant 3.3V LVTTL
1
GPIO4[TS2O]
I/O[O]
5V tolerant 3.3V LVTTL
1, 6
GPIO5:8[TS3:6]
I/O[O]
5V tolerant 3.3V LVTTL
1
GPIO9[TrcClk]
I/O[O]
5V tolerant 3.3V LVTTL
1
TestEn RcvrInh DrvrInh1:2 TmrClk
I I I I
2.5V CMOS w/pull-down 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 2 2 1
Trace Interface
[TS1E]GPIO1 [TS2E]GPIO2 Even Trace execution status. To access this function, software must toggle a DCR bit or General Purpose I/O. 5V tolerant 3.3V LVTTL
O[I/O]
1, 6
40
PowerPC 405GP Embedded Processor Data Sheet
Signal Functional Description
(Part 8 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 33 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 33 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 33.
Signal Name Description Odd Trace execution status. To access this function, software must toggle a DCR bit or General Purpose I/O. Odd Trace execution status. To access this function, software must toggle a DCR bit or General Purpose I/O. Trace status. To access this function, software must toggle a DCR bit or General Purpose I/O. Trace interface clock. A toggling signal that is always half of the CPU core frequency. To access this function, software must toggle a DCR bit or General Purpose I/O. I/O Type 5V tolerant 3.3V LVTTL
Notes
[TS1O]GPIO3
O[I/O]
1
[TS2O]GPIO4
O[I/O]
5V tolerant 3.3V LVTTL
1, 6
[TS3:6]GPIO5:8
O[I/O]
5V tolerant 3.3V LVTTL
1
[TrcClk]GPIO9
O[I/O]
5V tolerant 3.3V LVTTL
1
Ground pins
Ground Note: On the 456-ball packages, L11-L16, M11-M16, N11-N16, P11-P16, R11-R16, and T11-T16 are also thermal balls. On the 413-ball package, J11, J13, K11-K13, L11-L13, M11-N13, N11-N13, P11-P13, R11, and R13 are also thermal balls.
GND
OVDD pins
OVDD Output driver voltage--3.3V.
VDD pins
VDD Logic voltage--2.5V.
Other pins
Reserved Reserved--Except for Y5 (on the 413-ball package) or AF4, do not connect signals, voltage, or ground to these pins. Y5 (on the 413-ball package) and AF4 must be tied to OVDD or GND.
41
PowerPC 405GP Embedded Processor Data Sheet
Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device
Characteristic Supply Voltage (Internal Logic) Supply Voltage (I/O Interface) PLL Supply Voltage Input Voltage (2.5V CMOS receivers) Input Voltage (3.3V LVTTL receivers) Input Voltage (5.0V LVTTL receivers) Storage Temperature Range Case temperature under bias Note: All specified voltages are with respect to GND. Symbol VDD OVDD AVDD VIN VIN VIN TSTG TC Value 0 to +2.7 0 to +3.6 0 to +2.7 -0.6 to VDD + 0.6 -0.6 to OVDD + 0.6 -0.6 to OVDD + 2.4 -55 to +150 -40 to +120 Unit V V V V V V
C C
Package Thermal Specifications
The PPC405GP is designed to operate within a case temperature range of -40C to +85C. Thermal resistance values for the E-PBGA packages in a convection environment are as follows: Airflow ft/min (m/sec) Symbol Package--Thermal Resistance Unit
0 (0) 35mm, 456-balls--Junction-to-Case 35mm, 456-balls--Case-to-Ambient1 27mm, 456-balls--Junction-to-Case 27mm, 456-balls--Case-to-Ambient1 25mm, 413-balls--Junction-to-Case 25mm, 413-balls--Case-to-Ambient1 Note: 1. For a chip mounted on a JEDEC 2S2P card without a heat sink. 2. For a chip mounted on a card with at least one signal and two power planes, the following relationships exist: a. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board. b. TA = TC - Px CA, where TA is ambient temperature and P is power consumption. c. TCMax = TJMax - PxJC, where TJ Max is maximum junction temperature and P is power consumption. 100 (0.51) 2 13 2 16 1.5 15 200 (1.02) 2 12 2 15 1.5 13 C/W C/W C/W C/W C/W C/W
JC CA JC CA JC CA
2 14 2 18 1.5 17
42
PowerPC 405GP Embedded Processor Data Sheet
Recommended DC Operating Conditions
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability. Notes: 1. PCI drivers meet PCI specifications.
Parameter Logic Supply Voltage I/O Supply Voltage PLL Supply Voltage Input Logic High (2.5V CMOS receivers) Input Logic High (3.3V LVTTL receivers) Input Logic High (5.0V LVTTL receivers) Input Logic Low (2.5V CMOS receivers) Input Logic Low (3.3/5.0V LVTTL receivers) Output Logic High Output Logic Low 3.3V I/O Input Current (no pull-up or pull-down) Input Current (with internal pull-down) 5V Tolerant I/O Input Current 1 Input Max Allowable Overshoot (2.5V CMOS receivers) Input Max Allowable Overshoot (3.3V LVTTL receivers) Input Max Allowable Overshoot (5.0V LVTTL receivers) Input Max Allowable Undershoot Output Max Allowable Overshoot Output Max Allowable Undershoot Case Temperature Note: 1. See "5V-Tolerant Input Current" on page 44 Symbol VDD OVDD AVDD VIH VIH VIH VIL VIL VOH VOL IIL1 IIL2 IIL4 VIMAO25 VIMAO3 VIMAO5 VIMAU VOMAO VOMAU3 TC -0.6 -40 +85 -0.6 OVDD + 0.3 10 (@ 0V) 10 Minimum 2.3 3.0 2.3 1.7 2.0 2.0 0 0 2.4 0 Typical 2.5 3.3 2.5 Maximum 2.7 3.6 2.7 VDD OVDD 5.5 0.7 0.8 OVDD 0.4 10 400 (@ VDD) -650 VDD + 0.6 OVDD + 0.6 5.5 Unit V V V V V V V V V V Notes
A A A
V V V V V V
C
43
PowerPC 405GP Embedded Processor Data Sheet
5V-Tolerant Input Current
100
0 -100 Input Current (A)
-200 -300
-400
-500
-600 -700 0.0 1.0 2.0 3.0 4.0 5.0 Input Voltage (V)
Input Capacitance
Parameter 3.3V LVTTL I/O 5V tolerant LVTTL I/O PCI I/O Rx only pins Symbol CIN1 CIN2 CIN3 CIN4 Maximum 5.5 5 7 4 Unit pF pF pF pF Notes
44
PowerPC 405GP Embedded Processor Data Sheet
DC Electrical Characteristics
Parameter Active Operating Current (VDD)-200MHz Active Operating Current (VDD)-266MHz Active Operating Current (OVDD)-200MHz Active Operating Current (OVDD)-266MHz PLL VDD Input current Active Operating Power-200MHz Active Operating Power-266MHz Note: 1. Maximum power is characterized at VDD = 2.7V, OVDD = 3.6V, TC = 85C, across the silicon process (worse case to best case), while running an application designed to maximize power consumption. The specification at 200MHz corresponds to CPU = 200 MHz, PLB = 100MHz, OPB = EBC = 50MHz, PCI = 33.3MHz. The 266MHz maximum power was measured with CPU = 266.6MHz, PLB =133.3MHz, OPB = EBC = 66.6MHz, PCI = 33.3MHz. 2. AVDD should be derived from VDD using the following circuit: Symbol IDD IDD IODD IODD IPLL PDD PDD Minimum Typical 550 730 35 37 16 1.5 2.0 Maximum 670 880 37 40 23 2.01 2.61 Unit mA mA mA mA mA W W
VDD L1
AVDD
+ C1 C2 C3
AGND GND
L1 - 2.2H SMT inductor (equivalent to MuRata LQH3C2R2M34) or SMT chip ferrite bead (equivalent to MuRata BLM31A700S) C1 - 3.3 F SMT tantalum C2 - 0.1F SMT monolithic ceramic capacitor with X7R dielectric or equivalent C3 - 0.01 F SMT monolithic ceramic capacitor with X7R dielectric or equivalent
Test Conditions Clock timing and switching characteristics are specified in accordance with operating conditions shown in the table "Recommended DC Operating Conditions." For all signals other than PCI signals, AC specifications are characterized at OVDD = 3V and TC = 85C with the 50pF test load shown in the figure at right. For PCI signals there are two different test load circuits, one for the rising edge and one the falling edge as shown in the figures at right.
Output Pin
50pF
All signals other than PCI
Output Pin
PCI Rising edge
10pF
25
Output Pin
25 10pF
OVDD
PCI Falling edge
45
PowerPC 405GP Embedded Processor Data Sheet
Clocking Specifications
Symbol CPU PFC PTC SysClk Input SCFC SCTC SCTCS SCTCH SCTCL Clock input frequency Clock period Clock edge stability (phase jitter, cycle to cycle) Clock input high time Clock input low time 25 15 66.66 40 0.15 40% of nominal period 60% of nominal period 40% of nominal period 60% of nominal period MHz ns ns ns ns Processor clock frequency Processor clock period 200 or 266.66 5 or 3.75 MHz ns Parameter Min Max Units
Note: Input slew rate > 2V/ns MemClkOut Output MCOFC MCOTC MCOFC MCOTC MCOTCS MCOTCH MCOTCL Other Clocks VCOFC PLBFC PLBFC OPBFC OPBFC VCO frequency @ PFC = 200MHz PLB frequency @ PFC = 200MHz PLB frequency @ PFC = 266MHz OPB frequency @ PFC = 200MHz OPB frequency @ PFC = 266MHz 400 800 100 133.33 50 66.66 MHz MHz MHz MHz MHz Clock output frequency @ PFC = 200MHz Clock period @ PFC = 200MHz Clock output frequency @ PFC = 266MHz Clock period @ PFC = 266MHz Clock edge stability (phase jitter, cycle to cycle) Clock output high time Clock output low time 7.5 0.2 45% of nominal period 55% of nominal period 45% of nominal period 55% of nominal period 10 133.33 100 MHz ns MHz ns ns ns ns
Clocking Waveform
2.0V 1.5V 0.8V TCH TC TCL
46
PowerPC 405GP Embedded Processor Data Sheet
Spread Spectrum Clocking
Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC405GP. This controller uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the PPC405GP the following conditions must be met: * The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the PPC405GP with one or more internal clocks at their maximum supported frequency, the SSCG can only lower the frequency. * The maximum frequency deviation cannot exceed -3%, and the modulation frequency cannot exceed 40kHz. In some cases, on-board PPC405GP peripherals impose more stringent requirements (see Note 1). * Use the peripheral bus clock (PerClk) for logic that is synchronous to the peripheral bus since this clock tracks the modulation. * Use the SDRAM MemClkOut since it also tracks the modulation. Please refer to the application note Using a Spread Spectrum Clock Generator with the PowerPC 405GP for additional details. This application note is available on the IBM Microelectronics web site at http://www.chips.ibm.com. Notes: 1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that the connected device is running at precise baud rates. If an external serial clock is used the baud rate is unaffected by the modulation 2. Operation of the PPC405GP PCI Bridge is unaffected by the use of a SSCG. For PCI frequencies of 33.33 MHz and below the PCI controller supports synchronous mode operation. This is accomplished by strapping the PPC405GP for synchronous mode PCI and connecting the PCI bus clock to the PPC405GP SysClk input. For 33.33 MHz signalling, the PCI specification has no limitation on the amount of frequency deviation or modulation that may be applied to the PCI clock. Therefore, the PPC405GP SSCG requirements stated above take precedence. At PCI frequencies above 33.33 MHz, the PCI controller must be operated in asynchronous mode. When in asynchronous mode, the PCI bus clock must be driven into the PPC405GP PCIClk input. In this configuration the PCI controller supports the 66.66 MHz PCI clock specification which specifies a maximum frequency deviation of -1% at a modulation of between 30 kHz and 33 kHz. 3. Ethernet operation is unaffected. 4. IIC operation is unaffected. Caution: It is up to the system designer to ensure that any SSCG used with the PPC405GP meets the above requirements and does not adversely affect other aspects of the system.
47
PowerPC 405GP Embedded Processor Data Sheet
Peripheral Interface Clock Timings
Parameter PCIClk input frequency (asynchronous mode) PCIClk period (asynchronous mode) PCI Clock frequency (synchronous mode) PCI Clock period (synchronous mode - Note 2) PCIClk input high time PCIClk input low time EMCMDClk output frequency EMCMDClk period EMCMDClk output high time EMCMDClk output low time PHYTxClk input frequency PHYTxClk period PHYTxClk input high time PHYTxClk input low time PHYRxClk input frequency PHYRxClk period PHYRxClk input high time PHYRxClk input low time PerClk output frequency-200MHz PerClk period-200MHz PerClk output frequency-266MHz PerClk period-266MHz PerClk output high time PerClk output low time PerClk clock edge stability (phase jitter, cycle to cycle) UARTSerClk input frequency (Note 3) UARTSerClk period UARTSerClk input high time UARTSerClk input low time TmrClk input frequency-200MHz TmrClk period-200MHz TmrClk input frequency-266MHz TmrClk period-266MHz TmrClk input high time TmrClk input low time Note: 1. In asynchronous PCI mode the minimum PCIClk frequency is 1/8 the PLB Clock. Refer to the PowerPC 405GP Embedded Processor User's Manual for more information. 2. In synchronous PCI mode the PCI clock is derived from SysClk and the PCIClk input pin is unused. 3. TOPB is the period in ns of the OPB clock. The maximum OPB clock frequency is 50 MHz for 200MHz parts and 66.66MHz for 266MHz parts. - 2TOPB+2 TOPB+1 TOPB+1 - 20 - 15 40% of nominal period 40% of nominal period Min Note 1 15 25 30 40% of nominal period 40% of nominal period - 400 160 160 2.5 40 35% of nominal period 35% of nominal period 2.5 40 35% of nominal period 35% of nominal period - 20 - 15 45% of nominal period 45% of nominal period Max 66.66 Note 1 33.33 40 60% of nominal period 60% of nominal period 2.5 - - - 25 400 - - 25 400 - - 50 - 66.66 - 55% of nominal period 55% of nominal period 0.3 1000/(2TOPB+2ns) - - - 50 - 66.66 - 60% of nominal period 60% of nominal period Units MHz ns MHz ns ns ns MHz ns ns ns MHz ns ns ns MHz ns ns ns MHz ns MHz ns ns ns ns MHz ns ns ns MHz ns MHz ns ns ns
48
PowerPC 405GP Embedded Processor Data Sheet
Input Setup and Hold Waveform
SysClk 1.5 V TIS MIN Inputs 1.5V
TIH MIN
Valid
Output Delay and Float Timing Waveform
SysClk
1.5V TOV MAX TOH MIN
Outputs
1.5V Valid MAX MIN
TOF
Outputs
1.5V
49
PowerPC 405GP Embedded Processor Data Sheet
Notes: 1. In all of the following I/O Specifications tables a timing values of na means "not applicable" and dc means "don't care." 2. See "Test Conditions" on page 45 for output capacitive loading.
I/O Specifications--All speeds (Part 1 of 3) Notes: 1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz. 2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 3. For PCI, I/O H is specified at 0.9OVDD and I/O L is specified at 0.1OVDD. For all other interfaces, I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Input (ns) Signal Setup Time (TIS min) 3 3 dc 3 3 na 3 na 3 3 3 5 na na 3 3 na 100 na na na Hold Time (TIH min) 0 0 dc 0 0 na 0 na 0 0 0 0 na na 0 0 na 0 na na na 6 6 6 6 dc 6 6 6 na na na 6 6 settable Output (ns) Valid Delay (TOV max) 6 6 Hold Time (TOH min) 1 1 na 1 1 1 1 dc 1 1 1 na na na 1 1 2 Output Current (mA) I/O H (min) 0.5 0.5 na 0.5 0.5 0.5 na 0.5 0.5 0.5 0.5 na 0.5 0.5 0.5 0.5 9 9 9 9 9 9 9 na 4 4 4 1 1 1 na na na na na na 9 9 9 na I/O L (min) 1.5 1.5 na 1.5 1.5 1.5 na 1.5 1.5 1.5 1.5 na 1.5 1.5 1.5 1.5 6 6 6 6 6 6 6 na 6 6 6 na PHYRX PHYRX PHYRX EMCMDClk PHYTX PHYTX PHYTX PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk 1 1 2, async 2 2 2 2 2, async 2, async 2, async 2 2 2 2, async Clock Notes
PCI Interface
PCIAD31:0 PCIC3:0[BE3:0] PCIClk PCIDevSel PCIFrame PCIGnt0[Req] PCIGnt1:5 PCIIDSel PCIINT[PerWE] PCIIRDY PCIParity PCIPErr PCIReq0[Gnt] PCIReq1:5 PCIReset PCISErr PCIStop PCITRDY PCIClk PCIClk 1 1 async 1 1 1 1 async 1 1 1 1
Ethernet Interface
EMCMDClk EMCMDIO[PHYMDIO] EMCTxD3:0 EMCTxEn EMCTxErr PHYCol PHYCrS PHYRxClk PHYRxD3:0 PHYRxDV PHYRxErr PHYTxClk 1 OPB clock 1 OPB clock period + 10ns period 20 20 20 2 2 2
50
PowerPC 405GP Embedded Processor Data Sheet
I/O Specifications--All speeds (Part 2 of 3) Notes: 1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz. 2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 3. For PCI, I/O H is specified at 0.9OVDD and I/O L is specified at 0.1OVDD. For all other interfaces, I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Input (ns) Signal Setup Time (TIS min) na na na na na na na Hold Time (TIH min) na na na na na na na na na na na na na na na na na na na na na Output (ns) Valid Delay (TOV max) na na Hold Time (TOH min) na na Output Current (mA) I/O H (min) 19 19 12 12 12 12 12 12 12 12 12 na na 12 na 12 na na 12 na na I/O L (min) 12 12 8 8 8 8 8 8 8 8 8 na na 8 na 8 na na 8 na na async async async async async Clock Notes
Internal Peripheral Interface
IICSCL IICSDA UART0_CTS UART0_DCD UART0_DSR UART0_DTR UART0_RI UART0_RTS UART0_Rx UART0_Tx UART1_RTS/ UART1_DTR UART1_DSR/ UART1_CTS UART1_Rx UART1_Tx UARTSerClk
Interrupts Interface
IRQ0:6[GPIO17:23]
JTAG Interface
TCK TDI TDO TMS TRST
51
PowerPC 405GP Embedded Processor Data Sheet
I/O Specifications--All speeds (Part 3 of 3) Notes: 1. PCI timings are for asynchronous operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz. 2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 3. For PCI, I/O H is specified at 0.9OVDD and I/O L is specified at 0.1OVDD. For all other interfaces, I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Input (ns) Signal Setup Time (TIS min) dc Hold Time (TIH min) dc Output (ns) Valid Delay (TOV max) na Hold Time (TOH min) na Output Current (mA) I/O H (min) na I/O L (min) na Clock Notes
System Interface
DrvrInh1:2 GPIO1[TS1E] GPIO2[TS2E] GPIO3[TS1O] GPIO4[TS2O] GPIO5[TS3] GPIO6[TS4] GPIO7[TS5] GPIO8[TS6] GPIO9[TrcClk] Halt RcvrInh SysClk SysErr SysReset TestEn TmrClk dc dc dc dc dc dc dc dc na na na na 10 na na na na na na 1 na na
12
8
na na na 12 12 na na
na na na 8 8 na na
async
async async async async
52
PowerPC 405GP Embedded Processor Data Sheet
I/O Specifications--200MHz
Notes: 1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the command is used by SDRAM. 2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load. 3. SDRAM interface hold times are guaranteed at the PPC405GP package pin. System designers must use the PPC405GP IBIS model (available from www.chips.ibm.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring. 4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns. 5. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Input (ns) Signal Setup Time (TIS min) na na na na na na 2 na 2 na na na 5 dc 4 4 na 6 na 4 4 9 3 na na 5 na na 4 5 na 3 Hold Time (TIH min) na na na na na na 1 na 1 na na na 1 dc 1 1 na 1 na 1 1 1 1 na na 1 na na 1 1 na 1 Output (ns) Valid Delay (TOV max) 7.5 6.2 7.5 5.2 6.1 6.2 6.2 7.6 6.3 7.5 7.5 8 na 8 10 8 8 10 8 10 8 na 8 8 7 na 8 8 na na 0.9 na Hold Time (TOH min) 1 1 1 1 1 1 1 1 1 1 1 0 na 0 0 0 0 0 0 0 0 na 0 0 0 na 0 0 na na 0.7 na Output Current (mA) I/O H (minimum) 19 19 19 40 19 19 19 19 19 19 19 12 na 12 19 12 12 19 12 19 12 na 12 12 12 na 19 12 na na 19 na I/O L (minimum) 12 12 12 25 12 12 12 12 12 12 12 8 na 8 12 8 8 12 8 12 8 na 8 8 8 na 12 8 na na 12 na Clock Notes
SDRAM Interface
BA1:0 BankSel3:0 CAS ClkEn0:1 DQM0:3 DQMCB ECC0:7 MemAddr12:0 MemData0:31 RAS WE DMAAck0:3 DMAReq0:3 EOT0:3/TC0:3 PerAddr0:31 PerBLast PerCS0 PerCS1:7[GPIO10:16] PerData0:31 PerOE PerPar0:3 PerR/W PerReady PerWBE0:3 BusReq ExtAck ExtReq ExtReset HoldAck HoldPri HoldReq PerClk PerErr MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PLB Clk PerClk 4 1, 2 2 1, 2 2 2 2 2 1, 2 2 1, 2 1, 2
External Slave Peripheral Interface
External Master Peripheral Interface
53
PowerPC 405GP Embedded Processor Data Sheet
I/O Specifications--266MHz
Notes: 1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the command is used by SDRAM. 2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load. 3. SDRAM interface hold times are guaranteed at the PPC405GP package pin. System designers must use the PPC405GP IBIS model (available from www.chips.ibm.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring. 4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns. 5. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Input (ns) Signal Setup Time (TIS min) na na na na na na 1.5 na 1.5 na na na 4 dc 3 3 na 5 na 3 4 6.5 3 na na 4 na na 3 4 na 3 Hold Time (TIH min) na na na na na na 1 na 1 na na na 1 dc 1 1 na 1 na 1 1 1 1 na na 1 na na 1 1 na 1 Output (ns) Valid Delay (TOV max) 5.7 4.8 5.7 4.2 4.8 4.8 4.8 5.7 4.9 5.7 5.7 6 na 6 7.2 6 6 7.2 6 7.2 6 na 6 6 6 na 6 6 na na 0.9 na Hold Time (TOH min) 1 1 1 1 1 1 1 1 1 1 1 0 na 0 0 0 0 0 0 0 0 na 0 0 0 na 0 0 na na 0.7 na Output Current (mA) I/O H (maximum) 19 19 19 40 19 19 19 19 19 19 19 12 na 12 19 12 12 19 12 19 12 na 12 12 12 na 19 12 na na 19 na I/O L (minimum) 12 12 12 25 12 12 12 12 12 12 12 8 na 8 12 8 8 12 8 12 8 na 8 8 8 na 12 8 na na 12 na Clock Notes
SDRAM Interface
BA1:0 BankSel3:0 CAS ClkEn0:1 DQM0:3 DQMCB ECC0:7 MemAddr12:0 MemData0:31 RAS WE DMAAck0:3 DMAReq0:3 EOT0:3/TC0:3 PerAddr0:31 PerBLast PerCS0 PerCS1:7[GPIO10:16] PerData0:31 PerOE PerPar0:3 PerR/W PerReady PerWBE0:3 BusReq ExtAck ExtReq ExtReset HoldAck HoldPri HoldReq PerClk PerErr MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PLB Clk PerClk 4 1, 2 2 1, 2 2 2 2 2 1, 2 2 1, 2 1, 2
External Slave Peripheral Interface
External Master Peripheral Interface
54
PowerPC 405GP Embedded Processor Data Sheet
Strapping
When the SysReset input is driven low by an external device (system reset), the state of certain I/O pins is read to enable default initial conditions prior to PPC405GP start-up. The actual capture instant is the nearest SysClk edge before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. The recommended pull-up is 3k to +3.3V or 10k to 5V. The recommended pull-down is 1K to GND. These pins are use for strap functions only during reset. They are used for other signals during normal operation. The following table lists the strapping pins along with their functions and strapping options. The pin for the 456-ball package is listed first (for example, AF3), followed by the corresponding pin for the 413-ball package (for example, U8), which appears as AF3/U8.
PPC405GP Strapping Pin Assignments
Function PLL Tuning 1 for 6 M 7 use choice 3 for 7 < M
(Part 1 of 2)
Option AF3/U8 (UART0_Tx) Ball Strapping AF2/T8 AD16/AB15 (UART0_DTR) (UART0_RTS) 0 0 1 1 0 0 1 1 B15/B14 (DMAAck1) 0 1 0 1 C12/A8 (DMAAck3) 0 1 0 1 L24/J22 (EMCTxD2) 0 1 0 1 J26/F22 (EMCTxD0) 0 1 0 1 0 1 0 1 0 1 0 1
12 use choice 5 for 12 < M 32 use choice 6
Choice 1; TUNE[5:0] = 010001 Choice 2; TUNE[5:0] = 111011 Choice 3; TUNE[5:0] = 010011 Choice 4; TUNE[5:0] = 111101 Choice 5; TUNE[5:0] = 010101 Choice 6; TUNE[5:0] = 010110 Choice 7; TUNE[5:0] = 111110 Choice 8; TUNE[5:0] = 100100
0 0 0 0 1 1 1 1 D16/A17 (DMAAck0)
PLL Forward Divider
2
Bypass mode Divide by 3 Divide by 4 Divide by 6 PLL Feedback Divider
2
0 0 1 1 B14/A15 (DMAAck2)
Divide by 1 Divide by 2 Divide by 3 Divide by 4 PLB Divider from CPU 2 Divide by 1 Divide by 2 Divide by 3 Divide by 4 OPB Divider from PLB 2 Divide by 1 Divide by 2 Divide by 3 Divide by 4
0 0 1 1 P25/R23 (EMCTxD3) 0 0 1 1 L25/K21 (EMCTxD1) 0 0 1 1
55
PowerPC 405GP Embedded Processor Data Sheet
PPC405GP Strapping Pin Assignments
Function PCI Divider from PLB 2, 3 Divide by 1 Divide by 2 Divide by 3 Divide by 4 External Bus Divider from PLB
2
(Part 2 of 2)
Option Ball Strapping D18/A20 C20/C19 (GPIO1[TS1E]) (GPIO2[TS2E]) 0 0 1 1 K25/K20 (EMCTxErr) 0 1 0 1 K23/J21 (EMCTxEn) 0 1 0 1 AD2/N7 (UART1_RTS/ UART1_DTR) 0 1 0 1
Divide by 2 Divide by 3 Divide by 4 Divide by 5 ROM Width
0 0 1 1 AC2/N3 (UART1_Tx)
8-bit ROM 16-bit ROM 32-bit ROM Reserved ROM Location PPC405GP Peripheral Attach PPC405GP PCI Attach PCI Asynchronous Mode Enable Synchronous PCI Mode Asynchronous Mode PCI Arbiter Enable
3
0 0 1 1 U2/P4 (HoldAck) 0 1 Y3/U4 (ExtAck) 0 1 AF18/AB18 (GPIO4[TS2O])
Internal Arbiter Disabled Internal Arbiter Enabled Note:
0 1
1. The tune bits adjust parameters that control PLL jitter. The recommended values minimize jitter for the PLL implemented in the PPC405GP. These bits are shown for information only; and do not require modification except in special clocking circumstances such as spread spectrum clocking. For details on the use of Spread Spectrum Clock Generators (SSCGs) with the PPC405GP, visit the technical documents area of the IBM PowerPC web site. 2. Not all combinations of dividers produce valid operating configurations. Frequencies must be within the limits specified in "Clocking Specifications" on page 46. Further requirements are detailed in the Clocking chapter of the PowerPC 405GP Embedded Processor User's Manual. 3. Additional consideration must be given to pins that normally function as Trace signals. Improved design margin can be gained by using tri-state buffers instead of strapping resistors, and minimizing trace lengths and stubs.
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PowerPC 405GP Embedded Processor Data Sheet
Inside of back cover
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PowerPC 405GP Embedded Processor Data Sheet
(c) Copyright International Business Machines Corporation 1999, 2002
All Rights Reserved Printed in the United States of America, February 2002 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both: Blue Logic CoreConnect IBM Logo CodePack IBM PowerPC
Other company, product, and service names may be trademarks or service marks of others. Preliminary Edition (2/20/02) This document contains information on a new product under development by IBM. IBM reserves the right to change or discontinue this product without notice. This document is a preliminary edition of the PowerPC 405GP data sheet. Make sure you are using the correct edition for the level of the product. While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. The information contained in this document does not affect or change IBM product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document. IBM Microelectronics Division 1580 Route 52 Hopewell Junction, NY 12533-6351 The IBM home page is www. ibm.com. The IBM Microelectronics Division home is www.chips.ibm.com. SA14-2521-11
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